1. Field of the Invention
The present invention relates to a pulse width modulation (PWM) controlling circuit, more particularly, to a PWM controlling circuit for a switching power supply.
2. Description of Related Art
Various switching power supplies are available currently, which will be simply described in the following descriptions in conjunction with the accompanying drawings.
Referring to FIG. 1, which shows a conventional switching power supply, the switching power supply comprises a PWM controller 50, a switching transistor 51, a transformer with four secondary windings and four rectifying and filtering circuits respectively connected with the secondary windings. The switching power supply of FIG. 1 has four output voltages V01-V04. Only the first output voltage V01 is fed back to the PWM controller 50 as a feed-back signal. Accordingly, only the first output voltage V01 is regulated, and the regulation of each of the other output voltages V02, V03 and V04 is poor.
Focusing on the above problem, an improved design is provided, as shown in FIG. 2. The structure of FIG. 2 is similar to that of FIG. 1 except that a post regulator 60 is provided to each of the outputs V02, V03 and V04. Although the provision of the post regulators 60 can promote the regulation of the output voltages V02, V03 and V04, the conversion efficiency of each post regulator 60 is low resulting in a need for heat sink or the like, which occupy a lot of space.
FIG. 3 shows a conventional switching power supply, which is similar to that of FIG. 1 except that it utilizes two PWM controllers 50, 50'. As in the switching power supply of FIG. 1, the output voltage V01 is fed back to the first PWM controller 50, while the output voltage V04 is fed back to the second PWM controller 50'. Accordingly, the output voltages V01 and V04 appear to be regulated, but the regulation of the output voltages V02 and V03 is still poor. In addition, ideally, the two PWM controllers 50 and 50' should be exactly the same. However, this is impossible for the actual elements. Accordingly, oscillating frequencies of respective clock signals Clk1 and Clk2 of the respective two PWM controllers 50 and 50' are always slightly different, thereby causing a phenomenon of beat frequency.
Referring to FIG. 4, another conventional switching power supply provided for improving the phenomenon of beat frequency mentioned above is shown. In the structure of FIG. 4, the two PWM controllers 50 and 50' are connected with each other via a synchronization signal line 52, so that the two PWM controllers 50 and 50' can be synchronous with each other. However, such a design results in serious electromagnetic interference. Since the two PWM controllers are in on and off statuses synchronously, causing considerable instantaneous current (di) is generated to flow in the circuit, as shown in FIG. 5. Accordingly, noises and electromagnetic interference are serious problems for such a design.
Referring to FIG. 6, a further conventional switching power supply is shown. In this structure, a clock generator 53 is used to generate two signals, which are synchronous but different in phase, as clock signals for the respective two PWM controllers 50 and 50'. The two PWM controllers 50 and 50' accordingly operate alternately, thus the instantaneous current (di) is low, as shown in FIG. 7.
In application, the two PWM controllers 50, 50' and the clock generator 53 are integrated on a single IC, such as a dual current mode PWM controlling circuit 70 of a series UCC1810-3810 produced by UNITRODE, as shown in FIG. 8. The IC of the dual current mode PWM controlling circuit 70 comprises two output terminals OUT1, OUT2, an oscillator 71, a frequency divider 72, an inverter 73, two RS flip-flops 74, 75, two buffers 76, 77, and two leading edge blanking devices 78. Outputs from the output terminals OUT1 and OUT2 are synchronous but different in phase.
However, the cost of such an IC is very high. In addition, the two outputs from the output terminals OUT1 and OUT2 are inverse in phase, and the duty cycles of the respective output cannot exceed 50%.
Accordingly, the present invention is directed toward overcoming the above problem of the conventional dual current mode PWM controlling circuit.